This application claims the priority benefit of Taiwan application serial no. 87108193, filed May 26, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of Invention
The present invention relates to a method of manufacturing a buried gate. More particularly, the present invention relates to methods of manufacturing the buried gate of an electrically erasable programmable read only flash memory.
2. Background
Read only memory (ROM) is a type of non-volatile memory capable of retaining information even when the power is off. After the appearance of ROM, other types of ROMs, for example, the erasable programmable ROM (EPROM), whose memory content can be erased and re-programmed were developed. However, because the erasure of data within an EPROM requires the irradiation of ultra-violet light, its packaging cost is high. Furthermore, since all of the data or programs stored in an EPROM will be erased in a single operation, a time-consuming complete re-programming operation has to be carried out whenever any modification is required.
At present, a type of ROM known as an electrically erasable programmable ROM (EEPROM) are commonly used. The EEPROM is capable of modifying of data locally, and that data erasure and re-programming can be carried out in a bit-by-bit fashion. Moreover, the EEPROM can be read, erased and re-programmed iteratively. Recently, EEPROMs having an access speed of between 70 ns to 80 ns were developed by Intel Corporation with the name xe2x80x9cflash memoryxe2x80x9d. A flash memory has a structure somewhat like an EEPROM. However, the flash memory performs memory erasure in a block-by-block manner, and hence the speed of operation is faster. Often, memory erasure by the flash memory can be completed within 1 to 2 seconds, thereby saving time and manufacturing cost.
In general, the gate of a flash memory cell includes a two-layered structure. One of the layers, usually a polysilicon layer, serves as a floating gate used for storing electric charges. The other layer is a control gate serving to control the access of information. The floating gate is located beneath the control gate. Normally, the floating gate is in a xe2x80x9cfloatingxe2x80x9d state having no connection with other circuits. The control gate is generally connected to a word line. When data needs to be stored in a flash memory, a voltage is applied to the drain region and then a voltage higher than the applied drain voltage is applied to the control gate. Hot electrons will thus flow out from the source region and tunnel through the oxide layer near the drain region. The electrons are injected into the floating gate region and are trapped. Hence, the threshold voltage of the transistor is raised and the desired data is stored. When data are to be erased from a flash memory, a suitable positive voltage can be applied to the source region. The electrons trapped by the floating gate are tunneled out through the oxide layer. Hence, the stored data are erased, and that the floating gate of the transistor is returned to the previous storage state.
FIG. 1 is a cross-sectional view showing the transistor memory structure of a conventional flash ROM. As shown in FIG. 1, the memory unit mainly comprises a floating gate transistor. The gate of the transistor includes a two-layered structure. One of the layers is a floating gate 10, usually a polysilicon layer, serving as a region for storing electric charges. Another layer is a control gate 12 serving to control the access of information. In addition, there are tunneling oxide layer 14, gate oxide layer 16, drain region 18, source region 20. The floating gate 10 is located beneath the control gate 12. Normally, the floating gate is in a xe2x80x9cfloatingxe2x80x9d state having no connection with other circuits, whereas the control gate is generally connected to a word line.
The aforementioned flash ROM operates through the action of hot electrons. When data needs to be stored in the flash memory, a negative voltage is applied to the drain region 18 of the semiconductor substrate 22. Then, a voltage higher even than the voltage applied to the drain region 18 is applied to the control gate 12. Consequently, hot electrons will flow out from the source region 20 and tunnel through the oxide layer 14 near the drain region 18. Finally, the electrons tunnel through the tunneling gate 10 then into the floating gate region 10 where they are then trapped. Hence, the threshold voltage of the transistor is raised and the desired data is stored. On the other hand, when data need to be erased from a flash memory, a suitable positive voltage can be applied to the source region 20. Consequently, the trapped electrons within the floating gate 10 are tunneled out through the oxide layer 14 and into the semiconductor substrate 22. Hence, the stored data is erased, and the floating gate 10 of the transistor is returned to the previous storage state.
To reduce programming time and erase time for a flash ROM, the electric field in the tunneling region has to be increased. Conventionally, the method of increasing the electric field in the tunneling region is to increase the overlapping area between the floating gate and the control gate. In other words, the electric field is increased by increasing the coupling ratio of the flash ROM. In general, the method of increasing the coupling ratio is to utilize the space above the isolation region (including field oxide layer or shallow trench isolation region) for increasing the overlapping area between the floating gate and the control gate. However, since the current trend is moving towards high-level integration of semiconductor devices and memory devices, increasing overlapping area for increasing coupling ratio is contradictory to current development.
Alternatively, the electric field within the tunneling region 14 can be increased by increasing the operating voltage. But this alternative method of increasing the operating voltage for programming and erasing of flash ROM goes against current trends as well. This is because tremendous efforts has been put trying to lower heat output and noise interference for greater efficiency, and hence operating voltages are kept as low as possible. Moreover, increasing the operating voltage not only will lead to band-to-band tunneling between the floating gate and the drain, but also will waste power and leading to reliability problems. Furthermore, extra high-voltage pump circuits has to be added to amplify the input voltage if the operating voltage has to increase. This will increase area occupation of silicon chip and will lead to an increased circuit time delay.
In light of the foregoing, there is a need to provide an improved and more efficient method of forming buried floating gate flash ROM.
In view of the above, one method of dealing with the problems is to form a memory structure that has a buried floating gate. In other words, the floating gate of the flash memory is buried inside the substrate with the source/drain regions positioned on oppositing sides of the floating gate. The control gate is placed over the floating gate above the substrate surface. With this type of memory cell structure the charges tunnel from the control gate through the dielectric layer into the floating gate instead of tunnel through the thin dielectric layer and substrate then into the floating gate. Therefore the tunneling leakage current can be avoided and the tunneling speed between the floating gate and the control gate can be faster.
That is, the invention reduces the overlapping area between the control gate and floating gate while increasing the overlapping area between the floating gate and substrate. Therefore, the flash ROM will be scalable without relying on high charge pumping circuits. This is opposite to the conventional cells. Further, the floating gate is formed by a buried type of gate, hence programming speed of the flash ROM is increased while more memory cells can be packed within the same surface area of the chip.
Accordingly, the present invention is to provide a method of manufacturing flash ROM having buried floating gates. The method makes use of two trench-forming operations to form simultaneously buried floating gates and isolation structures. Through the method, the manufacturing of floating gate structures is greatly simplified. Moreover, the same method can be used to manufacture other buried conductive layers so that a multiple of buried conductive layers, each separated by isolation structures, can be formed at the same time.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a buried gate that can be applied to the manufacturing of the floating gate of a flash ROM. The method includes the steps of providing a substrate, and then forming a first trench in the substrate. Preferably, a first dielectric layer is formed over the substrate and the interior surface of the first trench, and then a first conductive layer is formed filling the first trench. Thereafter, a plurality of second trenches is formed within the first conductive layer and in the substrate. Finally, an insulation layer is deposited, filling the second trenches so that the first conductive layer is transformed into a plurality of floating gates.
Both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.